The present invention relates to apparatus for manufacturing of integrated circuits.
One of the basic problems in integrated circuit manufacturing is particulates. This problem is becoming more and more difficult, because of two trends in integrated circuit processing: First, as device dimensions become smaller and smaller, it is necessary to avoid the presence of smaller and smaller particles. This makes the job of making sure that a clean room is really clean increasingly difficult. For example, a clean room which is of class 1 (has one particle per cubic foot) for particles of one micron and larger may well be class 1000 or worse if particle sizes down to 100 angstroms are counted.
Second, there is increased desire to use large size integrated circuit patterns: for example, integrated circuit sizes larger than 50,000 square mils are much more commonly used now than they were five years ago.
Thus, particulates are not only an extremely important source of loss in integrated circuit manufacturing, but their importance will increase very rapidly in the coming years. Thus, it is an object of the present invention to provide generally applicable methods for fabricating integrated circuits which reduce the sensitivity of the process to particulate contamination.
One of the major sources of particulate contamination is human-generated, including both the particles which are released by human bodies and the particles which are stirred up by equipment operators moving around inside a semiconductor processing facility (front end). To reduce this, a general trend in the industry for several years has been to make more use of automatic transfer operations, wherein a technician can, for example, place a cassette of wafers into a machine, and then the machine automatically transfers the wafers, one by one, from the cassette through the machine (to effect the processing steps necessary) and back to the cassette, without the technician's having to touch the wafers.
However, the efforts in this direction have served to highlight the importance of a second crucial source of particulates, which is particulates generated internally by the wafers and/or transfer mechanism. That is, when the surface of the wafer jostles slightly against any other hard surface, some particulates (of silicon, silicon dioxide, or other materials) are likely to be released. The density of particulates inside a conventional wafer carrier is typically quite high, due to this source of particulates. Moreover, many of the prior art mechanisms for wafer transport will themselves generate substantial quantities of particulates.
The present invention advantageously solves this problem, by providing a wafer carrier wherein particulate generation during transport is reduced in several ways. First, the door of the vacuum carrier contains elastic elements to press the wafers lightly against the back of the carrier box. Thus, when the door of the box is closed, the wafers are restrained from rattling around, which reduces the internal generation of particulates. Second, the wafers are supported at each side by a slightly sloping shelf, so that minimal contact (line contact) is made between the wafer surface and the surface of the shelf. This reduces generation of particulates by abrasion of the surface of the wafer.
The present invention not only reduces generation of particulates in the carrier during transport and storage, but also advantageously reduces transport of particulates to the wafer face during transport and storage, by carrying the wafers face down, under a high vacuum. The prior art is not know to address this problem at all.
This wafer carrier design permits use with a wafer transport mechanism according to the present invention (and also disclosed in parent applications as filed) to provide a complete low-particulate wafer transport system.
The current state of the art wafer loading mechanisms used in the semiconductor industry consist primarily of three basic types: belt driven wafer transport, air track driven wafer transport, and arm driven wafer transport (using either vacuum coupling or nesting to hold the bottom or the edge of the wafer). However, all of these types of systems typically use face up wafer movement into and out of the carrier, vertical movement of the wafer carrier during the loading and unloading operations, wafer transfer under pressures ranging from atmospheric to low vacuum, and a requirement that wafers be unloaded in the reverse order of loading. The prior art methods accordingly have a number of important disadvantages, as follows:
First, wafers which are transported face up are more likely to catch particles generated by particle generation mechanisms inside the wafer carrier or inside the wafer loader unit.
Second, vertical movement of the wafer carrier during the loading and unloading operation creates many particles, due to rattling of the wafers in the carrier. These particles can fall directly onto the active face of adjacent wafers resting face up in the carrier.
Third, belt mechanisms will typically scrub the bottom of the wafer during loading and unloading operations, again creating many particulates due to abrasion.
Fourth, air track transport will stir many particulates around by air currents, and many of these particulates can come to rest on the active face of the wafer.
Fifth, the drive mechanisms of many loader modules are housed within the same area as the open wafer carrier will be, in close proximity to the wafers being processed. This has great potential for gross amounts of contamination.
Sixth, the mass of the carrier wafer combination changes as the wafers are loaded and unloaded, and this can affect the reliability and positioning of the wafer carrier vertical drive, particularly where large wafers (such as 150 millimeters or larger) are being handled.
Seventh, two loading modules are typically used for each processing station, so that one cassette is typically progressively loaded, and the wafers from this cassette which have been processed are loaded into a second cassette.
Eighth, loss of equipment utilization efficiency occurs every time a new cassette of wafers is loaded into or out of each processing station, since the machine must be idled while the cassette is removed.
The present invention provides advantageous solutions to all of the above problems, and achieves greatly improved low particulate wafer handling and loading operations.
One key advantage of the present invention is that wafers can be transported, loaded and unloaded without ever seeing atmospheric or even low vacuum conditions. This is extremely useful, because, at pressures of less than about 10.sup.-5 Torr, there will not be enough Brownian motion to support particulates of sizes larger than about 10 nm, and these particulates will fall out of this low-pressure atmosphere relatively rapidly.
FIG. 2 shows the time required for particles of different sizes to fall one meter under atmospheric pressure. Note that, at a pressure of 10.sup.-5 Torr or less, even 10 nm particles will fall one meter per second, and larger particles will fall faster. (Large particles will simply fall ballistically, at the acceleration of gravity.) Thus, an atmosphere with a pressure below 10.sup.-5 Torr means that particles ten nanometers or larger can only be transported ballistically, and are not likely to be transported onto the critical wafer surface by random air currents or Brownian drift.
The relevance of this curve to the present invention is that the present invention is the first to provide a way to transport wafers from one processing station to another, including loading and unloading steps, without ever exposing them to higher pressures than 10.sup.-5 Torr. This means that the wafers are NEVER exposed to airborne particulates, from the time they are loaded into the first vacuum processing station (which might well be a scrubbing and pumpdown station) until the time when processing has been completed, except where the processing step itself requires higher pressures (e.g. in conventional photolithography stations or for wet procesing steps). This means that the total possibilities for particulate collection on the wafers are vastly reduced.
A key element of this advantage is that the present invention provides a method and apparatus for loading and unloading a vacuum carrier under hard vacuum.
The present invention provides a load lock which includes an apparatus for opening a vacuum wafer carrier under vacuum, for removing wafers from the carrier in whatever random-access order is desired, and for passing the wafers one by one through a port into an adjacent processing chamber, such as a plasma etch chamber. Moreover, the load lock of the present invention is able to close and reseal the wafer carrier, so that the load lock itself can be brought up to atmospheric pressure and the wafer carrier removed, without ever breaking the vacuum in the wafer carrier.
A particular advantage of the preferred embodiments of the present invention is that the mechanical apparatus preferably used for wafer transfer is extremely compact. That is, by providing a transfer arm pivoted on an arm support, with gearing or a chain drive inside the arm support so that the rotation of the arm support causes twice as much rotation of the transfer arm with respect to the arm support, a compact apparatus is provided which can rest in the home position and require no more clearance than the length of the arm support in one direction, but can be extended, by a simple rotary shaft motion, out to the length of the arm support plus the length of the transfer arm in either of two directions.
A further advantage of the preferred embodiments of the present invention is that the motors used to extend the transfer arm and to change its elevation are both held inside an exhaust manifold, so that particles generated by these moving mechanical elements do not tend to reach the interior of the load lock chamber where wafers are exposed.
A further advantage of the invention is that a transfer arm is provided which can handle wafers face down with minimal damage to device areas caused by contact with the transfer arm.
A further advantage of the present invention is that the present invention provides a wafer transfer apparatus which can handle wafers with minimum generation of particulates caused by the handling operation.
A further advantage of the present invention is that the present invention provides a transfer apparatus which can handle wafers with essentially no generation of particulates due to abrasion, since essentially no sliding contacts are made.
Another advantage of the wafer transport mechanism of the present invention is that control is simplified. That is, the transfer arm preferably used has only two degrees of freedom, and position registration is provided so that the transfer arm control can be provided very simply (by use of stepper motors or comparable apparatus), without the need for sensors to detect the position of or forces on the arm.
A related advantage of the wafer transport mechanism of the present invention is that it is a stable mechanical system. That is, small errors in positioning do not accumulate, but are damped out by inherent negative feedback provided by some of the mechanical elements used. This also facilitates the advantage of simple control.
A further advantage of the present invention is that the wafer handling equipment used in the load lock takes up minimum volume. Since the load lock is of such small volume, vacuum cycling can be performed rapidly without requiring very expensive large vacuum pumps.
An even more important consequence of the volume efficiency of wafer transport according to the present invention is that the upper portion of the load lock (wherein the defect-sensitive surfaces of wafers being transferred will be exposed) will therefore have a small surface area. It is desirable to have as little surface area as possible within line-of-sight of the wafer surface, and it is also desirable to have as little surface area as possible in close proximity to the wafer surface, whether it is within line-of-sight or not. All surface area in the upper part of the load lock (i.e. the part above the exhaust manifold) presents two hazards: first, all surface area will desorb gasses, so that the more surface area is in the upper chamber the more difficult it will be to pull a hard vacuum. Second and more important, all surface area has the potential to hold adherent particulates, which can later be expelled by mechanical vibration or shock to fly ballistically onto the wafer surface, even under high vacuum. Thus, the volumetric efficiency of the load lock according to the present invention means that the potential for ballistic transport of particulates onto the wafer surface is reduced.
Moreover, the alternative embodiment disclosed in this continuation-in-part application has the further advantage that the wafers themselves do not ever see even the surfaces in the load lock which were exposed to particulates during loading of the carrier into the lock. In this embodiment the wafer carrier has a vacuum-sealable vertically removable cover, instead of a vacuum sealable hinged door, and, after the carrier is positioned in an upper chamber (the primary load lock) the carrier body is lowered from beneath the cover into a lower chamber while the cover remains in place and covers the aperture between upper and lower chambers. Thus, the wafer carrier body, and the wafers in it, not only never see dirty ambient atmosphere, they never even see surfaces which are exposed to dirty ambient atmosphere.
Another advantage resulting from the compactness of the wafer handling equipment in a load lock according to the present invention is that clean room floor space (which is very expensive) is not excessively consumed by such an apparatus.
Another advantage of the wafer carrier described in the present patent application is that this wafer carrier cannot inadvertently be opened outside a clean room. A substantial yield problem in conventional clean room processing is inadvertent or careless exposure of wafers to particulates by opening the wafer carrier outside the clean room environment. However, with the wafer carrier of the present invention this is inherently impossible, since the pressure differential on the door of the carrier holds it firmly shut except when the carrier is in vacuum. This is another reason why the present invention is advantageous in permitting easy transport and storage of wafers outside a clean room environment.
In a further class of embodiments of the present invention, a process module (which may optionally contain one process station or more than one process station) has more than one load lock according to the present invention attached to it. Thus, processing can continue on wafers transferred in from one load lock while the other load lock is being reloaded. Moreover, the provision of two transfer mechanisms means that, if a mechanical problem occurs with one transfer apparatus inside its load lock, the processing station can continue in production, using transfer through the other load lock, while a technician is summoned to correct the mechanical malfunction. Thus, this class of embodiments has the advantage of greater throughput. The load lock may be connected to a vacuum pump capable of pulling a vacuum higher than 10 to the -3 Torr.
According to the present invention there is provided: a method for fabricating integrated circuits, comprising the steps of: providing a plurality of wafers in a vacuum sealable wafer carrier box, said wafer carrier box comprising a cover which is vacuum sealed to a body thereof, said cover being removable from said body in a direction which is substantially normal to the plane of wafers supported in said body; placing said wafer carrier box into a vacuum sealable load lock upper chamber having a partial floor with an aperture therein and a stage positioned below said aperture in close proximity to said floor; pumping down said load lock upper chamber to a pressure less than 10.sup.-4 Torr; lowering said stage, so that said cover remains supported on said partial floor in said upper process chamber while said body including wafers is lowered into the lower chamber; transferring wafers in a desired sequence from said wafer carrier under vacuum to one or more selected process stations which are enclosed inside a connecting contiguous vacuum-tight space with said lower chamber until a desired sequence of processing operations has been completed; and then raising said stage to rejoin said wafer carrier body with said wafer carrier cover and again effect a vacuum seal therebetween; venting said upper chamber to ambient; and removing said wafer carrier from said upper chamber.
According to the present invention there is provided: a wafer carrier comprising: a wafer carrier body including supports which include ledges tapered to support a flat disk with substantially line contact and not area contact; said wafer carrier having said supports continuous with a base, said base including a vacuum seal thereon surrounding said side supports; said wafer carrier further comprising a cover, said cover being shaped to mate with said vacuum seal of said wafer carrier body, said cover, said vacuum seal, and said body defining a vacuum tight enclosure, said cover being removable from said body in a direction substantially normal to the plane of said vacuum seal.
According to the present invention there is provided: a wafer carrier comprising a body including sidewalls and also a cover closeable to make a vacuum-tight seal with said body, said sidewalls each having plural ledges thereon defining slots to hold wafers of a predetermined size, said ledges on said sidewalls having at least one surface thereof sloped to be at least 5 degrees out of parallel with the plane of said slots.
According to the present invention there is provided: a wafer carrier comprising a body including sidewalls and also a cover closeable to make a vacuum-tight seal with said body, said sidewalls each having plural ledges thereon defining slots to hold wafers of a predetermined size, said ledges on said sidewalls having at least one surface thereof sloped to be at least 5 degrees out of parallel with the plane of said slots; said carrier further comprising an elastic element on an inner surface thereof, said elastic element holding wafers of said predetermined size secure against free movement.
According to the present invention there is provided: a method of transporting integrated circuit wafers during fabrication, comprising the steps of: carrying said wafers under vacuum in a vacuum-tight carrier comprising a body including sidewalls and also a cover closeable to make a vacuum-tight seal with said body, said sidewalls each having plural ledges thereon defining slots to hold wafers of a predetermined size, said ledges on said sidewalls having at least one surface thereof sloped to be at least 5 degrees out of parallel with the plane of said slots.
According to the present invention there is provided: a method of transporting integrated circuit wafers during fabrication comprising the steps of: carrying said wafers under vacuum in a vacuum-tight carrier comprising a body including sidewalls and also a cover closeable to make a vacuum-tight seal with said body, said sidewalls each having plural ledges thereon defining slots to hold wafers of a predetermined size, said ledges on said sidewalls having at least one surface thereof sloped to be at least 5 degrees out of parallel with the plane of said slots: said carrier further comprising an elastic element on an inner surface thereof; said elastic element holding wafers of said predetermined size secure against free movement.
According to the present invention there is provided: a method of fabricating integrated circuits, comprising the steps of: transporting integrated circuit wafers during fabrication, comprising the steps of: carrying said wafers under vacuum in a vacuum-tight carrier comprising a body including sidewalls and also a cover closeable to make a vacuum-tight seal with said body; said sidewalls each having plural ledges thereon defining slots to hold wafers of a predetermined size, said ledges on said sidewalls having at least one surface thereof sloped to be at least 5 degrees out of parallel with the plane of said slots; said carrier further comprising an elastic element on an inner surface thereof, said elastic element holding wafers of said predetermined size secure against free movement.
According to the present invention there is provided: a method for fabricating integrated circuits, comprising the steps of: providing a plurality of wafers in a wafer carrier having a cover vacuum sealable to a body, said body including slots for holding wafers; placing said wafer carrier into a vacuum sealable load lock attached to a process module; pumping down said load lock to a pressure less than 10 to the -4 Torr, so that said vacuum seal between said carrier body and carrier cover releases; removing said carrier body from said cover, while said cover remains in said lock, so that wafers inside said carrier body are never exposed in line-of-sight to any substantial portion of the interior of said load lock; extending a transfer arm into said wafer carrier body, to remove a selected one of said wafers therefrom; transferring wafers in a desired sequence from said wafer carrier under vacuum to one or more selected process stations and back until a desired sequence of processing operations has been completed; and then closing said wafer carrier and raising the pressure of said load lock to approximately atmospheric, so that said wafers remain in vacuum inside said wafer carrier while said wafer carrier is held closed by differential pressure.